The research work will be centred on the development of radiation-hard integrated circuits for data transmission at very high data rates (~25.6 Gbps).

The engineer will be responsible for the development of architectures for communication ASICs and the design of high-speed data transmission CMOS circuits. Engineers with working experience in one or more of the following domains will be considered: High-Speed Differential Drivers (HSDD), Clock and Data Recovery (CDR) circuits, Phase Locked-Loops (PLL), Control Systems (CS), Optical Receivers (OR), Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converters.

Skills and/or knowledge

• Design, Simulation and Layout of CMOS integrated circuits
• RTL coding in Verilog
• Working knowledge of full-custom and/digital design flows
• Knowledge of at least one of the following:
  
  • Optical receivers;
  • High data rate drivers (line, laser and/or externa modulators);
  • PLL & CDR design;
  • ADC & DAC design;
  • Control systems;

You have a professional background in Electronics Engineering (or a related field) and have either:

• a Master's degree with 2 to 6 years of post-graduation professional experience;
• or a PhD with no more than 3 years of post-graduation professional experience.