We are looking for a digital ASIC design engineer to work on the next generation of advanced MAPS particle-detector ASICs for the CERN detector complex. You will contribute to the design, implementation, and verification of high-performance digital readout and control circuits that meet demanding targets in speed, density, power efficiency, and radiation tolerance, while collaborating closely with analog and verification specialists.

Be sure to meet the eligibility criteria

• You are a national of a CERN Member State or Associate Member State.
• By the application deadline, you have a master’s degree with 2 to 6 years of professional experience since graduation or a PhD with a maximum of 3 years of professional experience since graduation. You are not eligible with only a bachelor’s degree.
• You have never had a CERN fellow or graduate contract before.
• Please pay attention to the additional criteria and requirements for this specific position and mentioned above.