The project is based on an open-source RISC-V processing core and the CERN SOCRATES (System-On-Chip Radiation-Tolerant Ecosystem) framework for fault-tolerant SoC design. The successful candidate will contribute to the full development cycle, from requirements definition and system architecture to implementation, verification, and post-silicon validation

Your responsibilities

• Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC.
• Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology.
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core.
• Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework.
• Apply fault-tolerant design methodologies, including triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques.
• Participate in design verification activities and physical implementation, from RTL development through to tapeout.
• Contribute to post-silicon testing, characterisation, and validation following chip fabrication.

Be sure to meet the eligibility criteria

• You are a national of a CERN Member State or Associate Member State. Currently, we cannot consider applications from Pakistani, Lithuanian, Latvian, Cypriot and Croatian nationals, as the ceiling defined under Article II.5 of the Associate Membership Agreement has been reached.
• By the application deadline, you have a master’s degree with 2 to 6 years of professional experience since graduation or a PhD with a maximum of 3 years of professional experience since graduation. You are not eligible with only a bachelor’s degree.
• You have never had a CERN fellow or graduate contract before.
• Please pay attention to the additional criteria and requirements for this specific position and mentioned above.